module REG_PRJ_reg_rtl(
    ral_blk_REG_PRJ_sys_cfg_itf.regs sys_cfg_regs,
    ral_blk_REG_PRJ_sys_status_itf.regs sys_status_regs,
    ral_blk_REG_PRJ_sys_irq_itf.regs sys_irq_regs,

    input                                 pclk,
    input                                 presetn, 
    input   [`VMM_RAL_ADDR_WIDTH     -1:0]paddr,
    input                                 psel,
    input                                 penable,
    input                                 pwrite,
    input   [`VMM_RAL_DATA_WIDTH     -1:0]pwdata,
    input   [(`VMM_RAL_DATA_WIDTH/8) -1:0]pstrb,
    output                                pready,
    output  [`VMM_RAL_DATA_WIDTH     -1:0]prdata,
    output                                pslverr
);

vmm_ral_host_itf u_host_mst(pclk, presetn);

apb2hostif
u_apb2hostif(
             // Interfaces
             .mst                       (u_host_mst.master),
             // Outputs
             .pready                    (pready),
             .prdata                    (prdata[`VMM_RAL_DATA_WIDTH-1:0]),
             .pslverr                   (pslverr),
             // Inputs
             .pclk                      (pclk),
             .presetn                   (presetn),
             .paddr                     (paddr[`VMM_RAL_ADDR_WIDTH-1:0]),
             .psel                      (psel),
             .penable                   (penable),
             .pwrite                    (pwrite),
             .pwdata                    (pwdata[`VMM_RAL_DATA_WIDTH-1:0]),
             .pstrb                     (pstrb[(`VMM_RAL_DATA_WIDTH/8)-1:0]));
             
vmm_ral_host_itf u_sys_cfg_mst(pclk, presetn);
vmm_ral_host_itf u_sys_status_mst(pclk, presetn);
vmm_ral_host_itf u_sys_irq_mst(pclk, presetn);

ral_sys_REG_PRJ_rtl
u_sys_REG_PRJ(
    .sys_cfg(u_sys_cfg_mst.master),
    .sys_status(u_sys_status_mst.master),
    .sys_irq(u_sys_irq_mst.master),
    .hst(u_host_mst.slave)
);

ral_blk_REG_PRJ_sys_cfg_rtl u_blk_REG_PRJ_sys_cfg(.hst(u_sys_cfg_mst.slave), .usr(sys_cfg_regs));
ral_blk_REG_PRJ_sys_status_rtl u_blk_REG_PRJ_sys_status(.hst(u_sys_status_mst.slave), .usr(sys_status_regs));
ral_blk_REG_PRJ_sys_irq_rtl u_blk_REG_PRJ_sys_irq(.hst(u_sys_irq_mst.slave), .usr(sys_irq_regs));

endmodule